1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to structures that may be employed to analyze critical dimension variations and to pattern recognition marks that may be employed on devices manufactured using double patterning techniques.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Fabricating such circuit elements involves forming various “features” of the devices, such as gate electrode structures, metal lines, conductive contacts, etc. Such features are typically formed by depositing a layer of material, forming a patterned mask layer above the layer of material and thereafter performing an etching process through the patterned mask layer to define the feature. In other cases, a trench may be formed in a layer of material by performing an etching process through a patterned mask layer and thereafter a desired feature, e.g., a metal line, may be formed in the trench. The deposition, masking and etching techniques are performed using a variety of known deposition, etching and photolithographic tools and techniques.
Each of these features has a so-called “critical dimension,” which is typically the smallest size of a particular feature, e.g., the width of a line. As another example, for transistor devices, the critical dimension is gate length, which approximately corresponds to the width of the gate electrode that is positioned above the channel region of the device. Traditionally, a photoresist mask that is used in forming such features is formed by performing a single exposure through a reticle and thereafter developing the exposed photoresist layer that contains the “features” that will ultimately be transferred (by etching) to an underlying layer of material. That is, in past generation technologies, the feature size could be directly patterned in a photoresist mask layer in a single exposure process.
Over the recent years and continuing to present day, there has been a constant demand for electrical consumer devices with improved operating characteristics, such as operating speed, and for physically smaller devices. As a result, device designers have reduced the physical size of the various features that are used in manufacturing integrated circuit devices to increase their performance capability and to produce smaller devices with more functionality, e.g., cell phones. To be more specific, the gate length of current generation transistor devices has been reduced to about 25-30 nm, and further reductions are contemplated in the future. Advanced technology devices are being manufactured with feature sizes that approach or exceed the limits of existing 193 nm wavelength photolithography tools to reliably and repeatedly form such features to the desired feature size with the associated accuracy requirement that is inherent in manufacturing modern integrated circuit devices.
To overcome the limitations of current day photolithography tools and techniques, the semiconductor manufacturing industry has developed and employed several so-called double patterning techniques to be able to manufacture devices with features sizes that are smaller than can be patterned using a single exposure photolithography process. Double patterning generally involves the formation and use of two separate patterned photoresist mask layers instead of one to form the desired feature. Using these techniques, the second mask must be accurately aligned with the first mask. Two examples of known double patterning techniques includes a so-called LELE (Litho-Etch-Litho-Etch) process and a LFLE (Litho-Freeze-Litho-Etch) process. In addition to the requirement of a high degree of accuracy when using a double-mask double patterning process, as the density of the features formed on a chip increases, it is very important that the manufacturing process reliably and repeatedly produce device features where the critical dimensions of such features are maintained within very tight margins across the entirety of the wafer. Device manufacturers spend a great deal of time and effort to monitor critical dimension uniformity to insure that any critical dimension variations are within acceptable limits, and to identify potential processing errors. Device manufacturers also go to great lengths to insure that subsequent process layers are properly aligned with underlying features and layers so that the device will operate as intended.
By way of example, FIGS. 1A and 1B depict an illustrative prior art test structure 10 and a prior art pattern recognition mark 14, respectively, that have been employed in devices where features could be formed without resorting to double patterning techniques. For example, the prior art test structure 10 is a grating structure comprised of a plurality of densely-packed lines 12 and a single isolated line 12A. The features 12, 12A are all defined in a single mask layer and they are all formed at the same time by performing an etching process through the single mask layer. The features 12, 12A may correspond to gate electrodes that are formed at the same time as other operational gate electrodes are formed for an integrated circuit device. Such a test structure 10 may be used to analyze the critical dimension uniformity of a particular process flow. The test structure 10 has dense and isolated features so that manufacturers can analyze the effects, if any, on critical dimension uniformity as it relates to features formed in a densely packed area or an isolated area of the device. By stacking such test structures 10, the critical dimension uniformity of the process flow may be analyzed.
As noted previously, the prior art pattern recognition mark 14 was employed in devices where features could be directly patterned in a single exposure process, i.e., using a single patterned photoresist mask layer without resorting to the double patterning techniques discussed above. In this example, the pattern recognition mark 14 is in the form of a cross and it is comprised of a line feature 16 and an overlapping line feature 18 that are all defined in a single mask layer. The features 16, 18 may all be manufactured at the same time by performing an etching process through the single mask layer.
As noted above, the prior art test structure 10 and the pattern recognition mark 14 were manufactured using single-exposure, direct patterning techniques. FIG. 1C depicts a prior art test structure 20 that may be used to analyze or determine critical dimension uniformity in devices employing double patterning techniques, such as an LELE process. For example, the prior art test structure 20 is a grating structure comprised of a plurality of densely-packed lines 22A, 22B and a pair of isolated lines 24A, 24B positioned adjacent to one another. The features 22A, 22B, 24A and 24B are all formed using double patterning techniques. That is the features 22A and 24A are formed in the first masking layer while the features 22B and 24B are formed in a second masking layer. Ultimately, using double patterning techniques, the features in both the first and second mask will be transferred to a patterned hard mask layer. In practice, all of the features 22A, 22B, 24A, and 24B, e.g., lines or trenches, will be formed by performing a single etching process through the patterned hard mask layer. Such a test structure 20 may be used to analyze the critical dimension uniformity of a particular process flow. The test structure 20 has dense and isolated features so that manufacturers can analyze the effects, if any, on critical dimension uniformity as it relates to features formed in a densely packed area or an isolated area of the device.
The present disclosure is directed to structures that may be employed to analyze critical dimension variations and to pattern recognition marks that may be employed on devices manufactured using double patterning techniques.